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Honored Contributor
Honored ContributorJitter estimation on Arria II Gx devices
Hi everyone, I want to estimate jitter on various clocks used in my FPGA design. My device is an Arria II Gx FPGA. Input clock : 80 MHz Jitter : 1 ps (RMS) Output clock 1 : 100 M...
Altera_ForumHonored Contributor
Honored ContributorPLL generated jitter is one source of jitter. Other sources include io effect, reflections, etc. So ideally I would think that PLL spec is about PLL generated jitter in ideal case.
Two cascaded PLLs do not necessarily add up their jitter because every PLL has jitter tolerance so if the second PLL can bear it it may absorb it otherwise it certainly will make it worse.
