New Contributor
Frequent ContributorHi Aaronkwak,
Good day.
At the moment, I'm not able to replicate this issue from my end and still liaising with our internal team on this.
Q1) May I get the JESD204C configuration settings that you are using? a screenshot would be helpful.
Q2) May I know which Quartus version, operating system and OPN that you are using for your design?
Q3) May I know is your design derive from example design or reference design? Are you using Intel devkit or custom board?
Q4)Could you share with us your design?
Looking forward to hear back from you so that we can proceed for next step.
Thank you.
Best Regards,
ZH_Intel
New ContributorFirst of all, thank you for your reply.
Q1) May I get the JESD204C configuration settings that you are using? a screenshot would be helpful.
Sure!!!
Now Now tested setting parameter of JESD204C-classb1 RX
JESD204C-classb1 TX test complete.
Q2) May I know which Quartus version, operating system and OPN that you are using for your design?
Course.
Q3) May I know is your design derive from example design or reference design? Are you using Intel devkit or custom board?
Custom design referring to JESD204C example.
Board is Custom.
FPGA<--> RFIC(MAXLINEAR)
*. 4TX(491.52Msps/4LANE/16220.26@LANE):Test Complete
*. 2RX(245.76Msps/2LANE/16220.26@LANE): This Problem
*.2FeedBack(Rx)(491.52Msps/2LANE/16220.26@LANE): Same Problem
Q4)Could you share with us your design?
Need Full Project share???
This full project is many project license. (25G ethernet, ecpri, ORAN, JESD..) and HPS sub-system.
Have license issue? We can provide.
More information need???
Our team has a question.
After doing some checking and testing, we have some questions about the issue.
FPGA JESD RX(LSB First) <-- RFIC JESD TX(MSB First)
1. Is it correct that intel JESD204C RX Phy only supports LSB First?
MSB/LSB appears to be selectable in the data sheet/Register MAP, but cannot be controlled. The F-tile PMA datasheet says that the setting is Hardcoded. What is the truth?
2. In this case, SH_Lock can be a LOCK, but emb_lock may or may not be a lock, so we don't know why emb_lock is always a lock. I'd like to ask Intel's JESD204C expert.
3. We are working to resolve the issue (LSB/MSB difference). In the case of RFIC, it is not easy to solve the problem due to control issues. (MSB First --> LSB First)
Is it possible to change LSB first to MSB first in FPGA?
If you give us an answer, we will respond after a quick test.~~
