Occasional Contributorerror reported as
Error(19252): None of the output clocks of IOPLL "pll_test|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst" are connected. Please use at least one
All the pins in the PLL components are connected properly and never faced such issues in the previous megafunction.
can somebody suggest a solution
ContributorI suspect Quartus is removing any logic that you are driving from your PLL clock output signal. It will do this if no output pins on the device depend on that logic.
Make sure at least one FPGA pin is driven from the logic that is clocked from the PLL to ensure it's not removed by Quartus.
Cheers,
Alex
Occasional Contributorthanks Alex,
i think you are right.
Actually I assigned one of the output to a signal so that it can be connected to a different module.
thanks for the help.
Frequent ContributorHi Matt,
The above issue is due to the quartus optimization of the logic, make sure that when using the ip to connect to the logics
Occasional Contributorthanks RSree for your reply.
I want to keep the component in my design and i dont want to connect to any logic,(that is,connect the output to a signal)
I hope it was possible in megafunction.
can you suggest some possibility.
Frequent ContributorFrom the above discussion,I assume the quartus is optimizing the logic /IP . if that is the case , I am requesting to enable
The below options from assignment editor.
Preserver Fan-out Free Register Node :Yes
Netlist Optimization : Never Allow
Preserve Registers : Yes
