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Matt1's avatar
Matt1
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

issue with IOPLL in quartus prime 18.0

error reported as Error(19252): None of the output clocks of IOPLL "pll_test|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst" are connected. Please use at least one All the pins in the PLL componen...
a_x_h_75's avatar
a_x_h_75
Icon for Contributor rankContributor
6 years ago

I suspect Quartus is removing any logic that you are driving from your PLL clock output signal. It will do this if no output pins on the device depend on that logic.

Make sure at least one FPGA pin is driven from the logic that is clocked from the PLL to ensure it's not removed by Quartus.

Cheers,

Alex