Altera_Forum
Honored Contributor
10 years agoIs the clock buffer needed for every clock generated by PLL?
I am working on ARRIA V FPGA and I have the following design that I need to implement:
PLL has to generate 2 clocks : 62.5 and 12.5 MHz 1) My FPGA modules would be working at 62.5 MHz and I also need to send this clock to output clock pins. Do I need to use two clock buffers. i.e. external clock buffer for sending the clock to FPGA pins and regional clock buffer for clocking my internal modules. 2) 12.5 MHz clock is needed for clocking some moduels of FPGA for flash upgradation purposes. Do I need to place this clock into regional or global clock buffer? Also is it required that all the PLL clocks need to be placed onto clock buffers before it can be used in our modules? Please help