Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Is the clock buffer needed for every clock generated by PLL?

I am working on ARRIA V FPGA and I have the following design that I need to implement: PLL has to generate 2 clocks : 62.5 and 12.5 MHz 1) My FPGA modules would be working at 62.5 MHz and I also...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

How are you capturing your design? You don't need to instantiate any buffers, Quartus will take care of this for you.

1) If you use your 62.5MHz clock internally, Quartus will connect up this PLL output clock to appropriate clock routing resource. This will include a suitable buffer. If you also connect up this PLL output to I/O pins then, again, the required buffer will be inserted. You don't need to specifically instantiate either buffer.

2) The same goes for your 12.5MHz clock. Quartus will route this onto regional or global clock routing resources, with any buffers required, as necessary.

Cheers,

Alex