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Honored Contributor
Honored ContributorIs the clock buffer needed for every clock generated by PLL?
I am working on ARRIA V FPGA and I have the following design that I need to implement: PLL has to generate 2 clocks : 62.5 and 12.5 MHz 1) My FPGA modules would be working at 62.5 MHz and I also...
Altera_ForumHonored Contributor
Honored ContributorAgree with Alex, normally we would not need to add the ALTCLKCTRL buffer. QII will auto select the optimal clock network for you. In case you would like to specifically choose the clock network type, you can use ALTCLKCTRL to specify.
