Forum Discussion
Altera_Forum
Honored Contributor
10 years agoIs the clock buffer needed for every clock generated by PLL?
I am working on ARRIA V FPGA and I have the following design that I need to implement: PLL has to generate 2 clocks : 62.5 and 12.5 MHz 1) My FPGA modules would be working at 62.5 MHz and I also...
Altera_Forum
Honored Contributor
10 years agoArguably, there is no need for it (depending on your requirements). You certainly don't need one for an design to work.
As for what the ALTCLKCTRL core is for (straight from the user guide (https://www.altera.com/en_us/pdfs/literature/ug/ug_altclock.pdf)): --- Quote Start --- The common applications of using this megafunction are as follows: ■ Dynamic clock source selection ■ Dynamic power-down of a clock network --- Quote End --- Based on what you've written, I wouldn't expect you to need it. Cheers, Alex