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Altera_Forum's avatar
Altera_Forum
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13 years ago

Is it ok to build for a SV -2 speed grade and run on a -3 part?

Hey, - This post if for Rysc or anybody else who knows how timequest really works...

Thanks a ton for your excellent write-up on source synchronous analysis. It is the best I have seen. Looks like the outline has more sections...can't wait to read those when completed...

I am in the middle of a debate with a couple guys at work and figured I needed to ask someone who really seems to know how Altera timing models work. The debate is over speed grades. If you have a few minutes, an explanation would be a great help.

Assuming a Stratix V, if I were to build a design that meets timing on a -3 speed grade, can I always run it (safely) on a -2 device and never have to worry about some timing related error creeping in over valid -2 speed PVT?

We have a customer who purchased boards with -2 speed grades, but all new boards they want -3. However, they want to use the same build on both devices...they just want to use a new bit file targeted for the -3 as they have already deployed the system and don't want to keep track of which systems are which speed grade.

It feels to me like setup would be fine on a -2 if it passes with -3 timing analysis, but hold could pass on a -3, but violate when run on a -2. What would really happen?

I was also told that when Altera tests the chips they have no problem selling a -3 part that tested as a -2, they simply stamp it as such. This contradicts what I believe would be a hold timing error if I ran a build that passes a -3 on a very fast -2 part. Are they somehow trading off Fmax on the faster devices to allow more flexibility in chip sales?

The only way I know of that it could be 'safe' to build for a slow part and have it ALWAYS work on a fast part is if they used the same hold timing characteristics across all speed grades. In which case, hold analysis would have to be performed with the fastest device speed grade in all cases and setup analysis must be done with the timing numbers from the currently selected speed grade.

Is there something or a lot of things I am missing?

Thanks for your time!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    AFAIK Timequest always uses the worst case for hold requirements, whatever the speed grade. But I'm afraid you'll have a problem with the setup requirements, as a -2 grade is faster than a -3 and makes it easier to pass them.

    So if is the other way round. If you compile a project for -3 it can be run on a -2 without any problems, but a project compiled for a -2 may not run on a -3.
  • Altera_Forum's avatar
    Altera_Forum
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    By the way if you run the Timequest analyser (from the Tools menu) on your design and run the task "Set Operating Conditions" you will see in the list of timing models that only the two "slow" models that depend on the speed grade, but always the same "MIN" fast model, even if you change your device grade in the project settings. So I think that even if it isn't documented, it is safe to assume that the design will run on any faster FPGA model.