Is it ok to build for a SV -2 speed grade and run on a -3 part?

By the way if you run the Timequest analyser (from the Tools menu) on your design and run the task "Set Operating Conditions" you will see in the list of timing models that only the two "slow" models that depend on the speed grade, but always the same "MIN" fast model, even if you change your device grade in the project settings. So I think that even if it isn't documented, it is safe to assume that the design will run on any faster FPGA model.