Forum Discussion
FvM
Super Contributor
2 years agoHi,
I fear you don't yet understand the concept of defined IO standards.
The behaviour beyond specified VCCIO and logic voltages is simply undefined. You can't set IO standards with higher logic voltage than LVTTL/CMOS 3.3V and you shouldn't expect data or simulation support for it.
Does your intended device operation respect specified VCCIO voltage range and maximal ratings for input voltage? If not, you seem to look for trouble.
Input characteristics for extended voltage range are detailed described in IBIS files.