IO_SERDES_DPA error in place and route step

Hello,

I am trying to implement an RTL design which contains two LVDS SERDES receivers in SOFT-CDR mode . The received data will be redirected to LVDS SERDES transmitters and forwarded to ouput Pins. I tried both external/internal PLL options but in the place and route step the above error outcomes :

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IO_SERDES_DPA(s)).
Error (175020): The Fitter cannot place logic IO_SERDES_DPA that is part of LVDS SERDES Intel FPGA IP RX_SOFT_CDR_INTERNAL_altera_lvds_2000_zkkam5i in region (78, 173) to (78, 173), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The IO_SERDES_DPA name(s): lvds_conc_top_uut|lvds_gen[0].conc_dec_uut|u0|lvds_0|core|arch_inst|channels[0].soft_cdr.ioserdesdpa.serdes_dpa_inst
Info (175013): The IO_SERDES_DPA is constrained to the region (78, 173) to (78, 173) due to related logic
Info (175015): The I/O pad lvds_2n[0] is constrained to the location PIN_C32 due to: User Location Constraints (PIN_C32)
Info (14709): The constrained I/O pad contains this IO_SERDES_DPA
Info (175015): The I/O pad CLK_50_B3D is constrained to the location PIN_M27 due to: User Location Constraints (PIN_M27)
Info (14709): The constrained I/O pad drives a IOPLL, which drives this IO_SERDES_DPA
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (175005): Could not find a location with: DPRIO_ID of 121 (1 location affected)
Info (175029): IOSERDESDPA_X78_Y173_N7

When i use only one receiver and one transmitter the place and route step does not fail. I assume that the tool tries to place the second serdes_dpa in the same location that the first serdes dpa was placed , but i do not know how to overcome this.

Thanks