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epissadakis's avatar
epissadakis
Icon for New Contributor rankNew Contributor
3 years ago
Solved

IO_SERDES_DPA error in place and route step

Hello, I am trying to implement an RTL design which contains two LVDS SERDES receivers in SOFT-CDR mode . The received data will be redirected to LVDS SERDES transmitters and forwarded to ouput ...
  • mbc's avatar
    mbc
    3 years ago

    I think that is the problem.

    I had the same error when using pins from the same bank in two RX SERDES IP. Error got solved after changing the pins location of the inputs of one of the receivers, so using only one receiver IP for each bank works in my case.

AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Thank you for reaching out Intel FPGA Community.


Can you provide below information first? This is for better understanding.


  1. What is version of Quartus used for this project?
  2. Can you share the project file for us to replicate from our side?


Regards,

Aqid


epissadakis's avatar
epissadakis
Icon for New Contributor rankNew Contributor
3 years ago

Hi,

Unfortunately, i cannot share the project file. I use Quartus Prime Pro 22.1. As i understand there is only one IO_SERDES_DPA location per bank so when i try to instantiate more than one RX SERDES IP with different parameters it cannot be placed. Is this the problem ?

Regards

Manolis

  • mbc's avatar
    mbc
    Icon for New Contributor rankNew Contributor
    3 years ago

    I think that is the problem.

    I had the same error when using pins from the same bank in two RX SERDES IP. Error got solved after changing the pins location of the inputs of one of the receivers, so using only one receiver IP for each bank works in my case.