Forum Discussion
SK_VA
Occasional Contributor
Occasional ContributorIO_OBUF Placement and IC delay in timing path
Is there anyways we can constrain the placement of IO_OBUF so that it is closer to the pad.
How can we reduce the IC delay in the timing path?
17 Replies
KennyT_alteraSuper Contributor
You can attached your project.qar here?
SK_VAHi,
Even after using these options I am seeing the same delay from IO-OBUF to output pin.
Regards,
Sanju
- SK_VA
Hi,
I am using Cyclone IV with speed grade 8.These options are applicable for all devices and speed grades.Please suggest some document to get more information on these settings.
- KennyT_altera
You can go to the chip planner -> locate the IO -> cross probe it to resource property editor.
There you can see the delay.
Then, go to settings -> assignment editor -> look for d4 d5 delay and tune accordingly.
- SK_VA
Hi,
Thanks for the reply.
Can u please explain more on tuning d4 and d5 delay
- KennyT_alteraUnfortunately no. What you can do is 1) use fast input and out register. 2) tune the d4 and d5 delay.
