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SK_VA's avatar
SK_VA
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

IO_OBUF Placement and IC delay in timing path

Is there anyways we can constrain the placement of IO_OBUF so that it is closer to the pad. How can we reduce the IC delay in the timing path?
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

You can go to the chip planner -> locate the IO -> cross probe it to resource property editor.

There you can see the delay.

Then, go to settings -> assignment editor -> look for d4 d5 delay and tune accordingly.