SK_VAOccasional Contributor6 years agoIO_OBUF Placement and IC delay in timing path Is there anyways we can constrain the placement of IO_OBUF so that it is closer to the pad. How can we reduce the IC delay in the timing path?
SK_VAOccasional Contributor6 years agoHi,Thanks for the reply.Can u please explain more on tuning d4 and d5 delay
Recent DiscussionseFUSE : Agilex F series and AGilex I series PCIe cardIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAEP4CGX22CF19C8N Failure Short D8 to C8Cold Temperature IssueNeed Part EOL status(Active/Obsolete/Discontinued/NRND)