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Altera_Forum
Honored Contributor
Honored ContributorInvalid memory implementation
Please I need a help in following two questions:
First : I need to read from memory one element at a time, however, memory locations is not sequential so I need two variables as indicators. The problem is, when I use one indicator, the memory is implemented correctly, but when I add the other one ( k in example below ) the memory tend to be logic. IF rising_edge(clock) and show='1' THEN outvalues<=Memory1(i+k)-outvalues; -- +k here is the issue. k:=k+1; if k=3 then i:=i+8; end if; end if; So, what is the solution for such case? how I guide the synthesizer to implement it as a memory? Second question is: is it possible to initialize 2D array as an image ? , As I know MIF files are one dimension only. Thank you.4 Replies
Altera_ForumIf you're trying to infer a memory, you should be creating it as a 2D array, similar to this for a single port RAM:
ARCHITECTURE logic OF sp_ram IS TYPE mem_type IS ARRAY (0 TO 63) OF std_logic_vector (7 DOWNTO 0); SIGNAL mem: mem_type; BEGIN PROCESS (clock) BEGIN IF rising_edge(clock) THEN IF (wren = '1') THEN mem(to_integer(unsigned(address))) <= data; END IF; END IF; END PROCESS; q <= mem(to_integer(unsigned(address))); END ARCHITECTURE logic;- Altera_Forum--- Quote Start --- If you're trying to infer a memory, you should be creating it as a 2D array, similar to this for a single port RAM:
--- Quote End --- Thank you for replying; I already did that, but the problem is when I used two variables to indicate the address, memory couldn't be initialized. For 2D, what I meant is to make the initialization as 2D As: TYPE mem_type IS ARRAY (0 TO 63 , 0 TO 63) OF std_logic_vector (7 DOWNTO 0); However, this initialization is not possible to me since MIF file is 1D.ARCHITECTURE logic OF sp_ram IS TYPE mem_type IS ARRAY (0 TO 63) OF std_logic_vector (7 DOWNTO 0); SIGNAL mem: mem_type; BEGIN PROCESS (clock) BEGIN IF rising_edge(clock) THEN IF (wren = '1') THEN mem(to_integer(unsigned(address))) <= data; END IF; END IF; END PROCESS; q <= mem(to_integer(unsigned(address))); END ARCHITECTURE logic; - Altera_Forum
I don't understand why you're doing that. If you need 64 memories, use a for loop to create 64 mem_type arrays.
- Altera_Forum--- Quote Start --- I don't understand why you're doing that. If you need 64 memories, use a for loop to create 64 mem_type arrays. --- Quote End --- Sorry I didn't follow, would you give an example ? I am accessing the locations as 0,8,16,24 , 1,9,17,25 ; So normal for couldn'i make it as well. when I change the index memory stopped be initiated.
