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Altera_Forum's avatar
Altera_Forum
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8 years ago

Invalid memory implementation

Please I need a help in following two questions: First : I need to read from memory one element at a time, however, memory locations is not sequential so I need two variables as indicators. The...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

If you're trying to infer a memory, you should be creating it as a 2D array, similar to this for a single port RAM: 

ARCHITECTURE logic OF sp_ram IS
TYPE mem_type IS ARRAY (0 TO 63) OF
			std_logic_vector (7 DOWNTO 0);
SIGNAL mem: mem_type;
BEGIN
PROCESS (clock) BEGIN
	IF rising_edge(clock) THEN
		IF (wren = '1') THEN
			mem(to_integer(unsigned(address)))
				<= data;
		END IF;
	END IF;
END PROCESS;
q <= mem(to_integer(unsigned(address)));
END ARCHITECTURE logic;