invalid data received when communicating over ULPI bus

Hi,

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// High level of dir means that PHY transmitting, otherwise it is waiting for data from us.

assign ulpi_in_w = usb_ulpi_dir ? usb_ulpi_data : 8'b0;

assign usb_ulpi_data = usb_ulpi_dir ? 8'bZ : ulpi_out_w;

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Here “ulpi_in_w” will have either 8’bZ or 8’b0 and that will update the “ulpi_value” which decides VID_HIGH, PID_HIGH and PID_LOW, VID_LOW as in the following instantiation,

.ulpi_in(ulpi_in_w),--- > ulpi_value <= ulpi_in; ----> .ulpi_value(ulpi_value), ---> ulpi_value

case (ulpi_reg)
					REG_VID_LOW:
					begin
						vid <= ulpi_value;
						ulpi_reg <= REG_VID_HIGH;
					end
					
					REG_VID_HIGH:
					begin
						vid <= (ulpi_value << 8) | vid;
						ulpi_reg <= REG_PID_LOW;
					end
					
					REG_PID_LOW:
					begin
						pid <= ulpi_value;
						ulpi_reg <= REG_PID_HIGH;
					end
					REG_PID_HIGH:
					begin
						pid <= (ulpi_value << 8) | pid;
						request <= 0;
						state <= IDLE;
					end
				endcase

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Another anomaly that I noticed is that usb_ulpi_nxt is set on the same tick as I put usb_ulpi_data. As far as I understand from ulpi_doc_timing.png usb_ulpi_nxt bit should be set on the second tick after start of usb_ulpi_data transmission from us. This is very strange for me that usb_ulpi_nxt is set on the same tick as data started to be streamed from usb_ulpi_data.

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Check design code again.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)