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Altera_Forum's avatar
Altera_Forum
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8 years ago

invalid data received when communicating over ULPI bus

I have implemented simple FPGA-design that tries to read vid/pid register from ULPI PHY presented on DECA board over ULPI bus. But unfortunately my project is not working correctly. I am able t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Actually the problem appeared to be that I handled usb_ulpi_nxt too soon. Somehow it usb_ulpi_nxt started being active on the same clock front as I start usb_ulpi_data transmit. I think this is probably due to usb_ulpi_data are changed with some T_setup_time and usb_ulpi_nxt is checked with some T_clock_to_output time. It started working after I introduced one more state to delay usb_ulpi_nxt checking one tick later.