Occasional Contributor
Occasional ContributorWith question 1 I don't have a problem. Meantime I found that with EPM240T100 the compiler did not count the JTAG pins.
So questions 1 and 2 are solved.
For question 3 you say
Without the target, you've created a virtual clock, a clock created outside the FPGA that never actually enters the device, used for I/O timing analysis.
I don't know what the 'target' should be in my schematic. The pin planner connects the clock input named CLK to pin 37 of the chip named GCLK1. So CLK is entering the device. This part of my schematic is shown in the attachment.
I tried to extend the corresponding line within the sdc file according to your example:
create_clock -name {CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports GCLK1]
but the new compiler report contains the message
Warning (332174): Ignored filter at myTest.out.sdc(41): GCLK1 could not be matched with a port
I guess that the compiler will generate VHDL code from the schematic and in this code CLK is connected to a name which is the 'target'. But I don't know this name because I have no VHDL code for it. I only have the schematic.
Can you please give me tips how to find the needed 'target'?
Super ContributorI don't see a clock input in the part of your schematic you attached unless you're talking about "TRGI". The target should be whatever you've named it in the design. If it's TRGI, use that.
VHDL code has nothing to do with this. The tool interprets the schematic directly.
Occasional ContributorIn my former post I had attached a further image showing the clock input of my schematic but it was not transfered.
I try it again hoping that it will be transfered now.
