Interpretation of compiler report

1) Different I/O requirements don't make sense unless you removed I/O signals from the design, unless other pins like power or JTAG are being counted. Without seeing the design or the report, it's not really possible to determine what's going on here.

2) You're using latches instead of registers which by their very nature are combinational loops.

3) Your SDC is wrong. You have no target for your clock input. It should be something like this (depending on the name of your clock input pin):

create_clock -name {CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports clk]

Without the target, you've created a virtual clock, a clock created outside the FPGA that never actually enters the device, used for I/O timing analysis.