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Altera_Forum
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Honored Contributorinternal error:std_logic ports/signals must be width 1
I'm working with quartusII,v9.0.I want to add a component to the sopc builder.
when I try to generate my SOPC system.this error appears:"internal error:std_logic ports/signals must be width 1". My components are all written in VHDL. What does this error mean? Does anyone know how to fix the error? Does anyone know a workaround?9 Replies
Altera_ForumHello Farhaenis,
If u r using Quartus then goto Help and click messages. Here you see a list of possible messages that you get during compilation(errors/warnings). The error you get seems to be strange. Internal error doesn't do anything with std_logic. Anyways please check if you have any port width mismatch during instantiation. Normally internal error occurs when the compiler gets any unusual run time errors. Please check the SOPC user manual/documentation.- Altera_Forum
here is the error i found
- Altera_Forum
Here are steps i proceed to add the component.
- Altera_Forum
at ligne 226 and 230,type data and type adr are declared.(in this document)
- Altera_Forum
where are type data and type_adr declared?
- Altera_Forum
here is my code:(dwt 2d),you can see it.
thinks - Altera_Forum
you'll have to post some code so we can see what the problem is.
- Altera_Forum
i have seen this reply by wicks(sopc internal error: std_logic ports/signals must be width 1,in July 13th, 2009, 08:03 AM)(sorry i'm not able to post links) same error still occurs.
but i dont understand how to do it. I tried replacing all std_logic statements with std_logic_vector(0 downto 0), but the same error still occurs. - Altera_Forum
Never seen it before - it doesnt make sense, because std_logic is always width 1, becuase it is not a vector!
