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Altera_Forum's avatar
Altera_Forum
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16 years ago

internal error:std_logic ports/signals must be width 1

I'm working with quartusII,v9.0.I want to add a component to the sopc builder. when I try to generate my SOPC system.this error appears:"internal error:std_logic ports/signals must be width 1". ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

i have seen this reply by wicks(sopc internal error: std_logic ports/signals must be width 1,in July 13th, 2009, 08:03 AM)(sorry i'm not able to post links) same error still occurs.

but i dont understand how to do it.

I tried replacing all std_logic statements with std_logic_vector(0 downto 0), but the same error still occurs.