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Altera_Forum's avatar
Altera_Forum
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15 years ago

internal error:std_logic ports/signals must be width 1

I'm working with quartusII,v9.0.I want to add a component to the sopc builder. when I try to generate my SOPC system.this error appears:"internal error:std_logic ports/signals must be width 1". ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Never seen it before - it doesnt make sense, because std_logic is always width 1, becuase it is not a vector!