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Altera_Forum's avatar
Altera_Forum
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17 years ago

Internal clock generation

Hello frnds,

To put the problem very simple, I want to generate a clock of 10hz from 25 MHz. This 25 Mhz is being generated by PLL inside the FPGA and 10 Hz I want to generate

using VHDL code by using some sort of counter. But I am facing some difficulty as far as coding is concerned , being new to this field.

Please help me out by giving some ideas in terms of how should I implement the concept using VHDL code. Thanks in advance!

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You can use binary counter template from Quartus HDL editor context menu. Set MAX_COUNT to 2500000. Don't use the q binary output but generate a ckl10hz std_logic that is active for one input clock cycle, e. g. 

    IF cnt = 0 THEN 
  clk10hz = '1'; 
ELSE 
  clk10hz = '0'; 
END IF;
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The implementation depends a bit on how correct you want to be with the generated clock. If you need a clock that is exactly 10Hz, you will have to init the counter with a specific value.

    The better way to do it (if 11.9Hz is ok as well for your application) would be to implement a 21 Bit counter which runs continuously while using the upper bit as clock output. 

    
SIGNAL cnt : std_logic_vector(20 downto 0);
SIGNAL clk_10Hz : std_logic;
process (clk)
begin
   if (rising_edge(clk)) THEN
      cnt <= cnt + '1';
   end if;
end process;
clk_10Hz <= cnt (20);

    You will need to add the Libraries as follows for this to work:

    LIBRARY ieee;

    USE ieee.std_logic_1164.ALL;

    USE ieee.std_logic_unsigned.ALL;

    This is not tested though. Hope it helps anyways.

    If you need exactly 10Hz, you should use constants for the load value, count down to zero and toggle the clock signal when you reach zero.

    Anyways, just as a reminder: You should not use the 10Hz signal as internal clock. Better way to do it is to generate a clock enable signal on the rising edge of the 10Hz clock signal and use the 25MHz as clock (while enabling your registers with the clock enable).

    Regards,

    Lokla
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    My assumption was, that exactly 10 Hz should be provided, e. g. as a timebase.

    My suggested solution actually is intended to generate a clock enable (or qualifier), therefore it is active for one input clock cycle. For internal purposes, a gated clock should be strictly avoided.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Aye... I fully agree with you. Just been a bit slower with posting :)

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    Anyways, just as a reminder: You should not use the 10Hz signal as internal clock. Better way to do it is to generate a clock enable signal on the rising edge of the 10Hz clock signal and use the 25MHz as clock (while enabling your registers with the clock enable).

    --- Quote End ---

    --- Quote Start ---

    For internal purposes, a gated clock should be strictly avoided.

    --- Quote End ---

    There is more detail about clock dividers and clock enables at http://www.alteraforum.com/forum/showthread.php?t=2388.