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Altera_Forum
Honored Contributor
Honored ContributorInternal clock generation
Hello frnds, To put the problem very simple, I want to generate a clock of 10hz from 25 MHz. This 25 Mhz is being generated by PLL inside the FPGA and 10 Hz I want to generate ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Anyways, just as a reminder: You should not use the 10Hz signal as internal clock. Better way to do it is to generate a clock enable signal on the rising edge of the 10Hz clock signal and use the 25MHz as clock (while enabling your registers with the clock enable). --- Quote End --- --- Quote Start --- For internal purposes, a gated clock should be strictly avoided. --- Quote End --- There is more detail about clock dividers and clock enables at http://www.alteraforum.com/forum/showthread.php?t=2388.
