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Altera_Forum's avatar
Altera_Forum
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18 years ago

Internal clock generation

Hello frnds, To put the problem very simple, I want to generate a clock of 10hz from 25 MHz. This 25 Mhz is being generated by PLL inside the FPGA and 10 Hz I want to generate ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

You can use binary counter template from Quartus HDL editor context menu. Set MAX_COUNT to 2500000. Don't use the q binary output but generate a ckl10hz std_logic that is active for one input clock cycle, e. g. 

IF cnt = 0 THEN 
  clk10hz = '1'; 
ELSE 
  clk10hz = '0'; 
END IF;