Internal clock generation

The implementation depends a bit on how correct you want to be with the generated clock. If you need a clock that is exactly 10Hz, you will have to init the counter with a specific value.

The better way to do it (if 11.9Hz is ok as well for your application) would be to implement a 21 Bit counter which runs continuously while using the upper bit as clock output.

SIGNAL cnt : std_logic_vector(20 downto 0);
SIGNAL clk_10Hz : std_logic;
process (clk)
begin
   if (rising_edge(clk)) THEN
      cnt <= cnt + '1';
   end if;
end process;
clk_10Hz <= cnt (20);

You will need to add the Libraries as follows for this to work:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.ALL;

This is not tested though. Hope it helps anyways.

If you need exactly 10Hz, you should use constants for the load value, count down to zero and toggle the clock signal when you reach zero.

Anyways, just as a reminder: You should not use the 10Hz signal as internal clock. Better way to do it is to generate a clock enable signal on the rising edge of the 10Hz clock signal and use the 25MHz as clock (while enabling your registers with the clock enable).

Regards,

Lokla