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Altera_Forum
Honored Contributor
Honored ContributorInternal clock generation
Hello frnds, To put the problem very simple, I want to generate a clock of 10hz from 25 MHz. This 25 Mhz is being generated by PLL inside the FPGA and 10 Hz I want to generate ...
Altera_ForumHonored Contributor
Honored ContributorMy assumption was, that exactly 10 Hz should be provided, e. g. as a timebase.
My suggested solution actually is intended to generate a clock enable (or qualifier), therefore it is active for one input clock cycle. For internal purposes, a gated clock should be strictly avoided.
