Honored ContributorHi,
Is it possible the interface of ram IP core (from megawizard plug in manager) with niosII processor and VHDL as target HDL. I have generated NiosII processor with 4K of on chip ram.For this generated processor I want to connect RAM IP core. How to instantiate the niosII generated file into quartusII project. How to port map the instantiate file.. Pls help me.......
Honored ContributorIt's a lot easier to add your ram IP core as a component inside SOPC builder rather than using a component from the megawizard. If you really want to use a megawivard component, you'll have to write some wrapper HDL code to integrate it in SOPC builder.
Honored Contributorhi,
can you pls tell me how to do it. It will help me lot. thank youHonored ContributorHi Soloni,
I am not an expert but I have just successfully added on-chip SRAM to my design and it works fine. Here is the procedure I used: 1. In the Components Library pane of the SOPC Builder window expand the group "Memories and Memory Controllers". 2. Select On-Chip Memory (RAM or ROM) from the On-Chip sub-group. 3. A dialog box will open that lets you set the RAM configuration to suite your design. 4. Click Finish when you are done with the configuration and your newly created On-Chip RAM module will be added in the main SOPC pane. You can rename it if you prefer. 5. Connect the module to other modules in your design. 
(I already had a Nios II CPU module instantiated, so my on-chip memory was automatically connected to it.) Good Luck!Honored ContributorHi,
Thanks a lot for your suggestions. I have used ram block 1 ip core as new component in the sopc builder but getting some warnings. The followings are the warnings: <html>Warning: <b>.avalon_slave_0</b>: Signal <b>beginbursttransfer_n</b> appears 2 times (only once is allowed) <html>Warning: <b>.avalon_slave_0</b>: Slave with <b>beginbursttransfer</b> also needs <b>burstcount</b> for burst transfers <html>Warning: <b>.avalon_slave_0</b>: Should have <b>readdatavalid</b> signal for read burst transfers <html>Warning: <b>.avalon_slave_0</b>: Should have <b>waitrequest</b> signal for read burst transfers <html>Warning: <b>.avalon_slave</b>: Interface has no signals <html>Warning: <b>.avalon_slave</b>: Master has no read or write interface <html>Warning: <b>.avalon_slave_1</b>: Interface has no signals <html>Warning: <b>.avalon_slave_1</b>: Master has no read or write interface I dont know how to deal with these warnings. Can you pls help me to clear these warnings. Is it necessary to add on chip memory to Nios II processor during its creation.While creating Nios II processor it asks for reset vector and exception vector so thats why I added On chip memory. My task is to connect external ram to Nios II processor and read ram contents.I have attached the block diagram. I kindly request you to help me. thank you.......Honored ContributorHi,
I have used ram block 1 ip core as new component in the sopc builder but getting some warnings. The followings are the warnings: <html>Warning: <b>.avalon_slave_0</b>: Signal <b>beginbursttransfer_n</b> appears 2 times (only once is allowed) <html>Warning: <b>.avalon_slave_0</b>: Slave with <b>beginbursttransfer</b> also needs <b>burstcount</b> for burst transfers <html>Warning: <b>.avalon_slave_0</b>: Should have <b>readdatavalid</b> signal for read burst transfers <html>Warning: <b>.avalon_slave_0</b>: Should have <b>waitrequest</b> signal for read burst transfers <html>Warning: <b>.avalon_slave</b>: Interface has no signals <html>Warning: <b>.avalon_slave</b>: Master has no read or write interface <html>Warning: <b>.avalon_slave_1</b>: Interface has no signals <html>Warning: <b>.avalon_slave_1</b>: Master has no read or write interface I dont know how to deal with these warnings. Can you pls help me to clear these warnings. Is it necessary to add on chip memory to Nios II processor during its creation.While creating Nios II processor it asks for reset vector and exception vector so thats why I added On chip memory. My task is to connect external ram to Nios II processor and read ram contents.I have attached the block diagram. I kindly request you to help me. thank you.......Honored ContributorDo you want a memory bloc that can be both accessed from outside and from the Nios CPU? In that case you will need a dual port RAM, not a "RAM-1 port", have to write some HDL to connect one of the ports to an Avalon Slave interface, and use the whole as a new SOPC component.
If you just one a single port RAM connected to the Nios CPU then don't use the megawizard. Just add an on-chip memory component as fheineman explained.Honored Contributorhi,
I want to access(read) the contents of that RAM block1 through NIOS II processor. Pls can you tell me how to do this one? It will help me a lot....Honored ContributorDon't use the RAM block1, use an SOPC builder onchip memory as fheineman explained.
If you can't or don't want to use it, you'll have to give more details about what you want to do and why the on-chip memory doesn't work for you.Honored ContributorHi,
I added on chip memory and intialized with hex file.In hex file I have intialized some 250 values. I want to read these 250 values through niosII. I am attaching my main entity vhdl file . I kindly request you to check and correct it. I am not getting where is the problem...pls help me..Honored Contributorhi,
I want to connect external ram to the nios II processor thats why I used Megavizard plugin manager. I want to only read the contents of external ram through nios II processor. I am getting warnings while adding Ram block1 as component. Is there any other way to connect external ram to nios II processor? thank you..
