Altera_ForumHonored Contributor14 years agointerface with niosII processor Hi, Is it possible the interface of ram IP core (from megawizard plug in manager) with niosII processor and VHDL as target HDL. I have generated NiosII processor with 4K of on chip ram.Fo...Show More
Altera_ForumHonored Contributor14 years agohi, can you pls tell me how to do it. It will help me lot. thank you
Recent DiscussionsMAX10 Bitstreams AuthenticationArria 10 GX RX max intra-differential pair skewCyclone 10 GX development board collateralsAgilex 7 FPGA Availability on Cloud Platforms (AWS, Azure, GCP)?AGRW027R28A2I2V Thermal Model