Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

interface with niosII processor

Hi, Is it possible the interface of ram IP core (from megawizard plug in manager) with niosII processor and VHDL as target HDL. I have generated NiosII processor with 4K of on chip ram.Fo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi,

I have used ram block 1 ip core as new component in the sopc builder but getting some warnings. The followings are the warnings:

<html>Warning: <b>.avalon_slave_0</b>: Signal <b>beginbursttransfer_n</b> appears 2 times (only once is allowed)

<html>Warning: <b>.avalon_slave_0</b>: Slave with <b>beginbursttransfer</b> also needs <b>burstcount</b> for burst transfers

<html>Warning: <b>.avalon_slave_0</b>: Should have <b>readdatavalid</b> signal for read burst transfers

<html>Warning: <b>.avalon_slave_0</b>: Should have <b>waitrequest</b> signal for read burst transfers

<html>Warning: <b>.avalon_slave</b>: Interface has no signals

<html>Warning: <b>.avalon_slave</b>: Master has no read or write interface

<html>Warning: <b>.avalon_slave_1</b>: Interface has no signals

<html>Warning: <b>.avalon_slave_1</b>: Master has no read or write interface

I dont know how to deal with these warnings. Can you pls help me to clear these warnings.

Is it necessary to add on chip memory to Nios II processor during its creation.While creating Nios II processor it asks for reset vector and exception vector so thats why I added On chip memory.

My task is to connect external ram to Nios II processor and read ram contents.I have attached the block diagram. I kindly request you to help me.

thank you.......