interface code

Why have you got inputs floating?

Usually, floating inputs will mean things wont work properly.

Hi Sir,

Thanks again. what i did was design cir1 and cir3 in seperate vhdl files. then i designed another vhdl file named cir2.vhd. in this i did a port map.

In cir1 we have 3 inputs and 3 outputs. while in cir3 we have 3 i/ps and 4 o/ps.

which implies cir2 shall have 3 i/ps and 3 o/ps. But when i do a port map i only need to map o/ps of cir1 to i/ps of cir2 and o/p of cir2 to i/p of cir3. This basically means that i/p to cir1 and o/p to cir3 will be left floating and i am unable to use the portmap statement.

Any suggestions sir?

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Hello Sir,

Thanks for the reply. u r right they are all in different files viz cir1.vhd,cir2.vhd and cir3.vhd. Now u mentioned the entities at the top of the code for both cir1 and cir2.will i need to just declare the entities there or also the architecture as well?

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no, you dont need the entites at the top of cir2.vhd. They were just there to illustrate the port maps.

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So basically i shall write a new code for cir3 viz- cir3.vhd and follow the steps stated by you. also, as to "entity work.cir1" - this means that we need all the 3 vhdl files in the same work directory,right sir?

Thanks,

Vinod.

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they dont need to be the same working directory, just compiled into the same library. In VHDL the default local library is called "work".

Hello Sir,

Thanks for the reply. u r right they are all in different files viz cir1.vhd,cir2.vhd and cir3.vhd. Now u mentioned the entities at the top of the code for both cir1 and cir2.will i need to just declare the entities there or also the architecture as well?

So basically i shall write a new code for cir3 viz- cir3.vhd and follow the steps stated by you. also, as to "entity work.cir1" - this means that we need all the 3 vhdl files in the same work directory,right sir?

Thanks,

Vinod.

cir 2 is actually a wrapper around cir1 and cir3

here is an example (Im assuming cir1/2/3 are all separate files):

entity cir1 is
  port (
    input  : in  std_logic;
    output : out std_logic;
  );
end entity cir1;
  
  
entity cir3 is
  port (
    input  : in  std_logic;
    output : out std_logic;
  );
end entity cir1;
  
--To connect them:
entity cir2
  port (
    --add ports if you need them
  );
end entity cir2;
  
architecture struct of cir2 is
  signal cir1_to_cir3 : std_logic;
  signal cir3_to_cir1 : std_logic;
begin
  
  cir1_inst : entity work.cir1
  port map (
    input  => cir3_to_cir1,
    output => cir1_to_cir3
  );
  
  cir3_inst : entity work.cir3
  port map (
    input  => cir1_to_cir3,
    output => cir3_to_cir1
  );
    
end architecture struct;