interface code

cir 2 is actually a wrapper around cir1 and cir3

entity cir1 is
  port (
    input  : in  std_logic;
    output : out std_logic;
  );
end entity cir1;
  
  
entity cir3 is
  port (
    input  : in  std_logic;
    output : out std_logic;
  );
end entity cir1;
  
--To connect them:
entity cir2
  port (
    --add ports if you need them
  );
end entity cir2;
  
architecture struct of cir2 is
  signal cir1_to_cir3 : std_logic;
  signal cir3_to_cir1 : std_logic;
begin
  
  cir1_inst : entity work.cir1
  port map (
    input  => cir3_to_cir1,
    output => cir1_to_cir3
  );
  
  cir3_inst : entity work.cir3
  port map (
    input  => cir1_to_cir3,
    output => cir3_to_cir1
  );
    
end architecture struct;