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SnehalB's avatar
SnehalB
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3 years ago
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intel Cyclone V e , FPGA not reconfiguring to new flashed Image in EPCQ flash

Hi,

we are using intel cyclone v e device with EPCQ connected serial flash. we are using two IP core in our design 1st generic serial flash controller IP core for flashing EPCQ256 with .rpd image file and 2nd is reconfig IP core to configure fpga with new flash Image.

we are able to successfully flash image in QSPI through serial flash IP core as AS configuration. we flash Image at addr 0x100_0000 ( in IP core addr is 2bit shifted so addr used in IP core 0x40_000) as we are doing 4byte addressing mode page write , we increment address 0x100 (0x40) after every page write till all images is flashed

image format we used is .rpd also we checked the writing sequence in rpd , for eg if first 4 byte in .rpd is 0x12131415 (LSB -> MSB) in IP core we have used mem_wdata as 0x15141313 for writing as LSB is written first on transaction. we flashed after erasing the flash .

But after flashing is done , new image is not reconfiguring , status is nSTATUS error (0x2 value in 0x0 register of reconfig ip core), our reconfig page is set to 0x100_0000 correctly. New image is not able to reconfig even after successful flashing. Even tried with after bit reversal in each byte of config data but still new image is not able to reconfig.

1]request you to help us to solve the missing link to solve above issue?

2] also is there any way we can read flash memory after flashing for validating the flashed data, through quartus or any other tool?

thanks

Snehal B

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    3 years ago

    Hi, for CRC error, i think it could be due to the incorrect bitstream / bitstream order when loading it into the QSPI flash. I would suggest to select the appropriate data format when generating RPD file. You can select little endian for it. Otherwise, you need to do bit reversal.


9 Replies

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    1st thing 1st, is the image written correctly? To check the image file, you may read out the data stored and then compare with the rpd file.


  • SnehalB's avatar
    SnehalB
    Icon for New Contributor rankNew Contributor
    3 years ago

    hi how can we read back flash besides flash controller IP, is there any utility or method to read a FLASH via FPGA using jtag or serial interface.

    thanks & regards!

    Snehal B

  • SnehalB's avatar
    SnehalB
    Icon for New Contributor rankNew Contributor
    3 years ago

    hi YaunLi,

    So we checked reading back data after every write, so we find some error in read data.

    we checked in signal tap the data which we are sending to input to generic flash IP core avl_mem_writedata signal from fifo.

    we are doing 256byte write, and our data written is 0x504F4600, 0x00000100, 0x07000000... so on.

    But when we read back data from same address data is 0x504F4600, 0x10464700, 0x07000100...

    So we tried several iteration at different address with same data, everytime only first 4byte are write rest of data is wrong.

    Also data we gave input avl_mem_writedata is also correct. Design is running at 150Mhz whereas Flash SPI sclk is at 15Mhz.

    can you suggest us where we might be doing wrong?

    thanks & regards!

    Snehal B.

  • SnehalB's avatar
    SnehalB
    Icon for New Contributor rankNew Contributor
    3 years ago

    HI YaunLi,

    we are now hopefully able to write image correctly, but still not able to reconfig to new image, getting CRC error this time.

    We are flashing only half of the .rpd image as rest of the Image is FFFF... only .

    So I have few question ,

    1]is bit reversal need to be done in flashing .RPD image?

    2] Where is CRC located in .RPD image ?

    3] What could probably be wrong for getting CRC error ?

    Pls suggest some solution!

    thanks & regards!

    Snehal Buche

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi, for CRC error, i think it could be due to the incorrect bitstream / bitstream order when loading it into the QSPI flash. I would suggest to select the appropriate data format when generating RPD file. You can select little endian for it. Otherwise, you need to do bit reversal.


  • SnehalB's avatar
    SnehalB
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi we have tried to read back flashed data from QSPI flash and checked with original file, all bitstream on flash seems correctly flashed, but for required bitstream order we are not sure, we have tested for both little as well as big endian both case error is same.

    Also in generic flash ip core write data if 32 bit so for example flash data is 0x01020304 (0x01 being addr 0x00 data and so on) we are doing byte reversal as 0x04030201 as ip core write lsb byte first on qspi so for address alignment byte reversal done. (this we have done for both liitle as well big endian)

    I would suggest to select the appropriate data format when generating RPD file?

    --> can you suggest we data format will be appropriate

    --> Also do we use converted .rpd file or auto_rpd file for flashing?

    thanks & regards!

    Snehal B.

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Also in generic flash ip core write data if 32 bit so for example flash data is 0x01020304 (0x01 being addr 0x00 data and so on) we are doing byte reversal as 0x04030201 as ip core write lsb byte first on qspi so for address alignment byte reversal done. (this we have done for both liitle as well big endian)

    No, you dont need to do that. Just write byte-by-byte into QSPI flash will do. Use little endian is recommended.



  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


    • Dsriaknth's avatar
      Dsriaknth
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi

      Iam working with custom board with intel Cyclone 10 LP (10cl080yu484c6g) FPGA and Active serial device is EPCQ16A. here I am facing problem for generating JIC programming file for active serial configuration, I am getting error like “Size of file(s) in EPCQ16A exceeds memory capacity“. for this I made compress and I generated JIC programming file but it not programming into the active serial configurable devise (EPCQ16A). always Iam programming through JTAG connections and USB Blaster but Iam getting failed.

      for this my hardware configured MSEL pins value is (1101).

      ASDO, ASDI, AS nCS, AS DCLK pins are properly connected.

      please suggest me solution.

      thanks & regards.

      D. Srikanth