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SnehalB's avatar
SnehalB
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3 years ago
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intel Cyclone V e , FPGA not reconfiguring to new flashed Image in EPCQ flash

Hi, we are using intel cyclone v e device with EPCQ connected serial flash. we are using two IP core in our design 1st generic serial flash controller IP core for flashing EPCQ256 with .rpd image ...
  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    3 years ago

    Hi, for CRC error, i think it could be due to the incorrect bitstream / bitstream order when loading it into the QSPI flash. I would suggest to select the appropriate data format when generating RPD file. You can select little endian for it. Otherwise, you need to do bit reversal.


SnehalB's avatar
SnehalB
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3 years ago

hi YaunLi,

So we checked reading back data after every write, so we find some error in read data.

we checked in signal tap the data which we are sending to input to generic flash IP core avl_mem_writedata signal from fifo.

we are doing 256byte write, and our data written is 0x504F4600, 0x00000100, 0x07000000... so on.

But when we read back data from same address data is 0x504F4600, 0x10464700, 0x07000100...

So we tried several iteration at different address with same data, everytime only first 4byte are write rest of data is wrong.

Also data we gave input avl_mem_writedata is also correct. Design is running at 150Mhz whereas Flash SPI sclk is at 15Mhz.

can you suggest us where we might be doing wrong?

thanks & regards!

Snehal B.

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