New ContributorHi,
can i use the internal PLL of Cyclone 10 GX instead of using dedicated Clock input for DDR3 memory Clock?
All Development boards are using a dedicated clock, so is this mandatory?
Thanks!
Frequent ContributorHi ,
Kidnly follow the recommendation from the ug to connect to the clock to the emif Ip,
The PLL reference clock pin may be placed in the address and command I/O bank or in a data I/O bank, there is no implication on timing.
Reference page no: 20
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20116.pdf
Frequent ContributorHi ,
Kindly let me know if you need further assistance
New ContributorDear Mr. Rahul,
thank you very much for your answer. Now its clear for me.
BR!
