Integrating a custom component in SOPC [+IRQ]

Those functionalities (IRQ enable and clear) need to be done in your custom component, using additional registers. What I usually do in a custom component is to create two registers: a status register and a mask register.

Thanks for your help Daixiwen.

As i mentioned in a private msg to you.

   read_en  <= '1' when ((chipselect = '1') and (read = '1') and (byteenable = "1111"))  else '0';

I don't know how well it would integrate in your code but this is my general template for an Avalon memory mapped slave with IRQ:

	--! Main process
	Main: process(csi_Mem_Reset, csi_Mem_Clk) is 
				
	begin 
		if(csi_Mem_Reset = '1') then
			-- Initialize signals
			StatusRegister <= (others => '0');
			StatusInterruptMask <= (others => '0');
			
		elsif(rising_edge(csi_Mem_Clk)) then
			-- Avalon bus read
			if (avs_Conf_Read = '1') then
				
				case avs_Conf_Address is
		
					when AddressStatus =>
						ConfigReadData <= StatusRegister;
						
					when AddressInterruptMask =>
						ConfigReadData <= StatusInterruptMask;
					
					when others =>
						report "Bad address for read operation" severity error;
						
				end case; -- address
			end if; -- read
			-- Avalon bus write
			if (avs_Conf_Write = '1') then
				
				case avs_Conf_Address is
		
					when AddressStatus =>
						-- clear selected bits in the status register
						StatusRegister <= StatusRegister and (not avs_Conf_WriteData);
						
					when AddressInterruptMask =>
						StatusInterruptMask <= avs_Conf_WriteData;
						 
						 
					when others =>
						report "Bad address for write operation" severity error;
						
				end case; -- address
			end if; -- write
					
			-- update the status register when an event is detected
			if (something) then
				StatusRegister(n) <= '1';
			end if;
			
		end if; -- clock cycle
	end process; 

	-- IRQ generation
	ins_Interrupt_Irq <= 
		'0' when (unsigned(StatusRegister and StatusInterruptMask) = 0) 
		else '1';

Thank you so much

clk        : in  std_logic;
    reset_n    : in  std_logic;
    address    : in  std_logic_vector(3 downto 0);
    byteenable : in  std_logic_vector(3 downto 0);
    writedata  : in  std_logic_vector(31 downto 0);
    write      : in  std_logic;
    readdata   : out std_logic_vector(31 downto 0);
     irq            : out std_logic;
    read       : in  std_logic;
    chipselect : in  std_logic;

This is the read signal, and I'm using the nomenclature defined by Altera in the sopc manual (http://www.altera.com/literature/ug/ug_sopc_builder.pdf) (page 6-4). The only exception is the signal ConfigReadData which is connected to avs_Conf_ReadData outside the process.

Okay but my Linux recieves an IRQ from my SOPC custom component only when a pulse is detected right? If i keep my signal (irq) at one my linux won't see it.. am i wrong?

The way this works is: [list][*]The software runs normaly[*]A hardware component detects an event that should trigger an interrupt and raise the IRQ line[*]The CPU finishes processing the current instruction, and jumps to the ISR[*]The ISR reads the hardware status, acts accordingly, and returns[*]The CPU continues executing the application[/list]

Daixiwen i understand now, thank you so much for your help and your detailed explanation.

when AddressStatus => 						-- clear selected bits in the status register 						StatusRegister <= StatusRegister and (not avs_Conf_WriteData);

Daixiwen i understand now, thank you so much for your help and your detailed explanation.