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Altera_Forum
Honored Contributor
14 years agoI don't know how well it would integrate in your code but this is my general template for an Avalon memory mapped slave with IRQ:
--! Main process
Main: process(csi_Mem_Reset, csi_Mem_Clk) is
begin
if(csi_Mem_Reset = '1') then
-- Initialize signals
StatusRegister <= (others => '0');
StatusInterruptMask <= (others => '0');
elsif(rising_edge(csi_Mem_Clk)) then
-- Avalon bus read
if (avs_Conf_Read = '1') then
case avs_Conf_Address is
when AddressStatus =>
ConfigReadData <= StatusRegister;
when AddressInterruptMask =>
ConfigReadData <= StatusInterruptMask;
when others =>
report "Bad address for read operation" severity error;
end case; -- address
end if; -- read
-- Avalon bus write
if (avs_Conf_Write = '1') then
case avs_Conf_Address is
when AddressStatus =>
-- clear selected bits in the status register
StatusRegister <= StatusRegister and (not avs_Conf_WriteData);
when AddressInterruptMask =>
StatusInterruptMask <= avs_Conf_WriteData;
when others =>
report "Bad address for write operation" severity error;
end case; -- address
end if; -- write
-- update the status register when an event is detected
if (something) then
StatusRegister(n) <= '1';
end if;
end if; -- clock cycle
end process;
And outside the process (but it could be inside too, it would add one cycle delay) -- IRQ generation
ins_Interrupt_Irq <=
'0' when (unsigned(StatusRegister and StatusInterruptMask) = 0)
else '1';
I hope this helps