Integrate the Opencores's I2C ip into SOPC

I have done the process as the trout writes, and generated a symbol named I2cCore. The I2cCore occupys 32 8-bit address. But in the 32 addresses, I find that I can only write 4 of them, why? I am confused that which are the registers? Is there anything I omitted? By the way, in the nios2 core, I have integrated cup, onchip_memory, timer, pio, epcs_controller, jtag and I2cCore. Does anyone can help me?

Hi:

--------------------------------------------
-- Description VHDL d'une interface I2C maître
-- FM 28/06/2005
--------------------------------------------
-- Déclaration des bibliothèques
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--------------------------------------------
-- Déclaration de l'entité
entity oc_i2c_master_top is
    port(
        -- Signaux du bus Avalon
        address:       in unsigned(2 downto 0);
        readdata:      out std_logic_vector(7 downto 0);
        writedata:     in std_logic_vector(7 downto 0);
        write:         in std_logic;
        chipselect:    in std_logic;
        clk:           in std_logic;                     -- Entrée horloge
        reset_n:       in std_logic;                     -- Entrée de RESET (actif à l'état bas)
        irq:           out std_logic;
        waitrequest_n: out std_logic;
        
        -- Sortie I2C
        scl: inout std_logic;                -- i2c clock line output
        sda: inout std_logic                 -- i2c data line output
     );
end oc_i2c_master_top;
--------------------------------------------
-- Déclaration de l'architecture comportementale "algorithmique" de l'entité
architecture bhv of oc_i2c_master_top is
component i2c_master_top is
    generic(
  ARST_LVL : std_logic                          -- asynchronous reset level
    );
    port (
  -- wishbone signals
  wb_clk_i  : in  std_logic;                    -- master clock input
  wb_rst_i  : in  std_logic;                    -- synchronous active high reset
  arst_i    : in  std_logic;                    -- asynchronous reset
  wb_adr_i  : in  unsigned(2 downto 0);         -- lower address bits
  wb_dat_i  : in  std_logic_vector(7 downto 0); -- Databus input
  wb_dat_o  : out std_logic_vector(7 downto 0); -- Databus output
  wb_we_i   : in  std_logic;               -- Write enable input
  wb_stb_i  : in  std_logic;                    -- Strobe signals / core select signal
  wb_cyc_i  : in  std_logic;               -- Valid bus cycle input
  wb_ack_o  : out std_logic;                    -- Bus cycle acknowledge output
  wb_inta_o : out std_logic;                    -- interrupt request output signal
  -- i2c lines
  scl_pad_i     : in  std_logic;                -- i2c clock line input
  scl_pad_o     : out std_logic;                -- i2c clock line output
  scl_padoen_o  : out std_logic;                -- i2c clock line output enable, active low
  sda_pad_i     : in  std_logic;                -- i2c data line input
  sda_pad_o     : out std_logic;                -- i2c data line output
  sda_padoen_o  : out std_logic                 -- i2c data line output enable, active low
    );
end component;
signal scl_pad_i     : std_logic;
signal scl_pad_o     : std_logic;
signal scl_padoen_o  : std_logic;
signal sda_pad_i     : std_logic;
signal sda_pad_o     : std_logic;
signal sda_padoen_o  : std_logic;
begin
    i2c_top : i2c_master_top
        generic map ( ARST_LVL => '0')
        port map (
            wb_adr_i  => address,
            wb_dat_i  => writedata,
            wb_dat_o  => readdata,
            wb_we_i   => write,
            wb_stb_i  => chipselect,
            wb_cyc_i  => chipselect,
            wb_inta_o => irq,
            wb_clk_i  => clk,
            wb_ack_o  => waitrequest_n,
            wb_rst_i  => '0',
            arst_i    => reset_n,
            
            scl_pad_i    => scl_pad_i,
            scl_pad_o    => scl_pad_o,
            scl_padoen_o => scl_padoen_o,
            sda_pad_i    => sda_pad_i,
            sda_pad_o    => sda_pad_o,
            sda_padoen_o => sda_padoen_o
        );
    scl <= scl_pad_o when (scl_padoen_o = &#39;0&#39;) else &#39;Z&#39;;
    sda <= sda_pad_o when (sda_padoen_o = &#39;0&#39;) else &#39;Z&#39;;
    scl_pad_i <= scl;
    sda_pad_i <= sda;
end architecture bhv;

Hi,

The I2C slave model of OC is not synthesizable, but the master seems to work.

Thank U!!