Integrate the Opencores's I2C ip into SOPC

Hi:

I have designed a IPcore which is belown:

library ieee;

use ieee.std_logic_1164.all;

entity ad574 is

port(D :IN STD_LOGIC_VECTOR(15 DOWNTO 0);

address: in std_logic_vector(1 downto 0);

CLK ,STATUS,read: IN STD_LOGIC;--״̬»úʱÖÓCLK£¬AD574״̬ÐźÅSTATUS

byteenable: in std_logic_vector(3 downto 0);

chipselect: in std_logic;

CE,CS,A0,RC,K12X8: OUT STD_LOGIC; --AD574¿ØÖÆÐźÅ

Q : out STD_LOGIC_VECTOR(31 DOWNTO 0));

end ad574;

architecture behav of ad574 is

type state is (st0, st1, st2, st3,st4);

signal current_state,next_state :state:=st0;

signal data_reg_select: std_logic;

signal control_reg_select: std_logic;

SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);

SIGNAL lock: STD_LOGIC;

begin

K12X8 <= &#39;1&#39;;

process(address,chipselect)

begin

data_reg_select<=&#39;0&#39;;

control_reg_select<=&#39;0&#39;;

if chipselect=&#39;1&#39; then

case address is

when "00" => data_reg_select<=&#39;1&#39;;

when "01" => control_reg_select<=&#39;1&#39;;

when others => null;

end case;

end if;

end process;

process(current_state,status) --»ù±¾ÈÎÎñÉè¼Æ(״̬ÄÚÐźű仯)

begin

case current_state is

when st0 =>CE<=&#39;0&#39;;CS<=&#39;1&#39;; A0<=&#39;1&#39;;RC<=&#39;1&#39;;LOCK<=&#39;0&#39;;next_state <= st1;

when st1 =>CE<=&#39;1&#39;;CS<=&#39;0&#39;; A0<=&#39;0&#39;;RC<=&#39;0&#39;;LOCK<=&#39;0&#39;; next_state <= st2;

when st2 =>CE<=&#39;1&#39;;CS<=&#39;0&#39;; A0<=&#39;0&#39;;RC<=&#39;0&#39;;LOCK<=&#39;0&#39;;

IF (STATUS=&#39;1&#39;) THEN next_state <= st2;

ELSE next_state <= st3;

END IF ;

when st3 =>CE<=&#39;1&#39;;CS<=&#39;0&#39;; A0<=&#39;0&#39;;RC<=&#39;1&#39;;LOCK<=&#39;0&#39;; next_state <= st4;

when st4 =>CE<=&#39;1&#39;;CS<=&#39;0&#39;; A0<=&#39;0&#39;;RC<=&#39;1&#39;;LOCK<=&#39;1&#39;; next_state <= st0;

when others =>CE<=&#39;0&#39;;CS<=&#39;1&#39;; A0<=&#39;1&#39;;RC<=&#39;1&#39;;LOCK<=&#39;0&#39;;next_state <= st0;

end case;

end process;

PROCESS (clk,control_reg_select,chipselect) --¿ØÖƼĴæÆ÷¿ØÖÆת»»¹ý³Ì

BEGIN

IF ( clk&#39;EVENT AND clk=&#39;1&#39;) THEN

if (control_reg_select and chipselect)=&#39;1&#39; then

current_state <= next_state;

end if;

END IF;

END PROCESS ;

process(lock) --Êý¾Ý¿ØÖƼĴæÆ÷²Ù×÷

BEGIN

IF LOCK=&#39;1&#39; AND LOCK&#39;EVENT THEN

if byteenable(0)=&#39;1&#39; then data_reg(7 downto 0)<=d(7 downto 0);end if;data_reg<=d;

if byteenable(1)=&#39;1&#39; then data_reg(15 downto 8)<=d(15 downto 8);end if;

if byteenable(2)=&#39;1&#39; then data_reg(23 downto 16)<="00000000";end if;

if byteenable(3)=&#39;1&#39; then data_reg(31 downto 24)<="00000000";end if;

END IF;

END PROCESS ;

process(read,clk,data_reg_select,chipselect) --NIOS×ÜÏßͨѶ

begin

if clk&#39;event and clk=&#39;1&#39; then

if (read and data_reg_select and chipselect)=&#39;1&#39; then

Q <=data_reg;

else

Q<=(others=>&#39;Z&#39;);

end if;

end if ;

end process;

END behav;

now I integerate the IP to sopc , and the base address of the IP is :0x02000008 and the end address is 0x0200000f , the generation of the system is successful . but when I built the software about the system above on the NiosII IDE , but there is error and display that the range of the IP ---ad16bit is out of the range of the address , what is it? while I change the "Q : out STD_LOGIC_VECTOR(31 DOWNTO 0));" to " Q : out STD_LOGIC_VECTOR(15 DOWNTO 0)); " the error is disappeared. why?

and how can I write the drivers of the IP core ? who can help me?