Honored Contributor
Honored Contributor
i looked for the an 333 and it's no longer available, does anyone have a modified oc_i2c_master.h file or some hints on how to modify the .h file to work with sopc builder?
thanks --- Quote End --- There is a new document present on Altera web site who describe how to create a NIOS II / SOPC Builder component: Quartus II Development Software Handbook v5.0 Volume 4: SOPC Builder. It is available here (http://www.altera.com/literature/hb/qts/qts_qii5v4.pdf) or go to quartus literature page (http://www.altera.com/literature/lit-qts.jsp). I add opencores I2C master component to SOPC Builder, but to do that I have created an additionnal VHDL file because SOPC Builder seems to have problem with the STD_LOGIC GENERIC parameters.
--------------------------------------------
-- Description VHDL d'une interface I2C maître
-- FM 28/06/2005
--------------------------------------------
-- Déclaration des bibliothèques
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--------------------------------------------
-- Déclaration de l'entité
entity oc_i2c_master_top is
port(
-- Signaux du bus Avalon
address: in unsigned(2 downto 0);
readdata: out std_logic_vector(7 downto 0);
writedata: in std_logic_vector(7 downto 0);
write: in std_logic;
chipselect: in std_logic;
clk: in std_logic; -- Entrée horloge
reset_n: in std_logic; -- Entrée de RESET (actif à l'état bas)
irq: out std_logic;
waitrequest_n: out std_logic;
-- Sortie I2C
scl: inout std_logic; -- i2c clock line output
sda: inout std_logic -- i2c data line output
);
end oc_i2c_master_top;
--------------------------------------------
-- Déclaration de l'architecture comportementale "algorithmique" de l'entité
architecture bhv of oc_i2c_master_top is
component i2c_master_top is
generic(
ARST_LVL : std_logic -- asynchronous reset level
);
port (
-- wishbone signals
wb_clk_i : in std_logic; -- master clock input
wb_rst_i : in std_logic; -- synchronous active high reset
arst_i : in std_logic; -- asynchronous reset
wb_adr_i : in unsigned(2 downto 0); -- lower address bits
wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
wb_we_i : in std_logic; -- Write enable input
wb_stb_i : in std_logic; -- Strobe signals / core select signal
wb_cyc_i : in std_logic; -- Valid bus cycle input
wb_ack_o : out std_logic; -- Bus cycle acknowledge output
wb_inta_o : out std_logic; -- interrupt request output signal
-- i2c lines
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end component;
signal scl_pad_i : std_logic;
signal scl_pad_o : std_logic;
signal scl_padoen_o : std_logic;
signal sda_pad_i : std_logic;
signal sda_pad_o : std_logic;
signal sda_padoen_o : std_logic;
begin
i2c_top : i2c_master_top
generic map ( ARST_LVL => '0')
port map (
wb_adr_i => address,
wb_dat_i => writedata,
wb_dat_o => readdata,
wb_we_i => write,
wb_stb_i => chipselect,
wb_cyc_i => chipselect,
wb_inta_o => irq,
wb_clk_i => clk,
wb_ack_o => waitrequest_n,
wb_rst_i => '0',
arst_i => reset_n,
scl_pad_i => scl_pad_i,
scl_pad_o => scl_pad_o,
scl_padoen_o => scl_padoen_o,
sda_pad_i => sda_pad_i,
sda_pad_o => sda_pad_o,
sda_padoen_o => sda_padoen_o
);
scl <= scl_pad_o when (scl_padoen_o = '0') else 'Z';
sda <= sda_pad_o when (sda_padoen_o = '0') else 'Z';
scl_pad_i <= scl;
sda_pad_i <= sda;
end architecture bhv;
