Insufficient GPIO Pins for 32-Bit Adder Implementation on DE0 Nano SoC

You need to use internal register(s) to store the values in A, B, and/or SUM.

If you do that, you could load the input A, B registers with just two or three signals (CLOCK plus one or two DATA inputs).
Serial shift in the data inputs using 32 (or 64) clocks on the DATA line(s).
So just two or three pins.

Then you have 33 outputs needed for SUM plus COUT.

Total of 3 + 33 = 36 signals total, less than 40 with some spares...

And if you want even fewer, you could store the SUM/COUT in a register and shift it out serially also.
With a LOAD/SHIFT line, a CLOCK line, and a DATAOUT line just three lines needed.

So if you want to really minimize I/O you could do it in 3+3=6 lines (or even 3+2=5 lines with a shared CLOCK line).

OR

If you don't want to do serial shifting, you could define a 32b bus that is input/output.

And then have a CLOCK and 3 MODE bits that say what is on the 32b bus.

For example:

So this would require 32 (or 33 for COUT) data bits and 4 control bits, for a total of 37 GPIOs.