Input signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5

Hi,

We tried using the logic analyzer and the signal quality degraded. I started seeing the FTDI chip missing clock signals.

I agree with your assessment that, mismatch of delays, accumulated over the connector, cable and then board trace would be causing this. When I try to sample the 66MHz FTDI clock and data and control interface, I do see about 2 cycle (5 ns) variation in the data settling to steady value on signaltap. There could be similar variations on the RXF_N signal. I am out of ideas on how to make this work, as to what special consideration I need in the design or if it is just a matter of constraining it. Let me know if you have any suggestions. I am also commuicating with FTDI support. Will update with further development.

Best,

Bharat