Input signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5

Hi

As suggested here earlier, I changed FTDI interface within the FPGA to operate on the negative edge of FTDI clock. I still see the same issues i.e. RXF_N is asserted (low) and the data on the data bus is not valid data. The FTDI interface along with its clock is sampled with 400 mhz clock.

Best

Bharat