Forum Discussion
BKB
Occasional Contributor
Occasional ContributorInput signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5
Hi, I am trying to interface the FTDI601 USB Bridge (https://ftdichip.com/products/ft601q-b/) to the Stratix 10 1SG10MHN3F74C2LG_U1/U2 FPGA on our design board. The reference clock for the interface...
BKBOccasional Contributor
Occasional ContributorHi
As suggested here earlier, I changed FTDI interface within the FPGA to operate on the negative edge of FTDI clock. I still see the same issues i.e. RXF_N is asserted (low) and the data on the data bus is not valid data. The FTDI interface along with its clock is sampled with 400 mhz clock.
Best
Bharat
