Initial process does not run?

Adding a little code here could help us help you.

The code looks like this:

bit Array;
initial begin
  byte i;
  for (i=20; i>=0; i--)
    Array = 1;
end
always @ (posedge PLL)
  begin
    // Array value returns 0 at all elements here
  end

"initial" is only used in test benches, it can not be used for code running in an FPGA.

bit Array;
initial begin
  byte i;
  for (i=20; i>=0; i--) begin
    Array = 1;
  end
end
always @ (posedge PLL)
  begin
    // Array value returns 0 at all elements here
  end

I am coding in SystemVerilog. Quartus does not report any syntax error, so I think the for loop structure is fine. The initial process affects some other variables except array type. :confused:

Initial block will be synthesized as POR state for signals or possibly as initial values for block RAM.

Thank you for the replies.

I have created a nested loop to initial the array, but I failed to assign it's value.

bit Array ;
initial begin
  byte i, j;
  for (i=20; i>=0; i--)
    for (j=20; j>=0; j--)
      Array = 0;
  for (i=20; i>=0; i--)
    Array = 1;
end
always @ (posedge PLL)
  begin
    // Array returns 0 at all elements here
  end

I could reproduce a Quartus problem with initial blocks. What I see is this:

module ram_with_init(
  output reg  q,
  input  d,
  input  write_address, read_address,
  input we, clk
);
  reg  mem ;
  integer i;
  initial begin
    for (i = 0; i < 32; i = i + 1)
      mem = i;
  end
  always @ (posedge clk) begin
    if (we)
      mem <= d;
    q <= mem;
  end
endmodule

I have just contacted Altera Support, but they refused to file my request because my account was not registered under a company/university name, and my e-mail address was not associated with a company/university. :(

I have a single dimension array implemented in register not working:

reg  Array ;
initial begin
  byte i, j;
  for (i=63; i>=0; i--)
    Array = 0;
  for (i=63; i>=0; i--)
    Array = 1;
end
always @ (posedge PLL)
  begin
    // Array returns 1 at Array only.
  end