Forum Discussion
Altera_Forum
Honored Contributor
13 years ago"initial" is only used in test benches, it can not be used for code running in an FPGA.
Although I'm not much of a verilog guy, I think the for loop is constructed incorrectly. Trybit Array;
initial begin
byte i;
for (i=20; i>=0; i--) begin
Array = 1;
end
end
always @ (posedge PLL)
begin
// Array value returns 0 at all elements here
end