Initial process does not run?

I could reproduce a Quartus problem with initial blocks. What I see is this:

- If the array is implemented in registers, initial blocks like in the present example are working without limitations.

- If the array infers RAM, initial blocks should be converted to memory initialization files, as stated in the Quartus handbook:

--- Quote Start ---

In Verilog HDL, you can use an initial block to initialize the contents of an inferred

memory. Quartus II integrated synthesis automatically converts the initial block into a

.mif for the inferred RAM. Example 6–19 shows Verilog HDL code that infers a simple

dual-port RAM block and corresponding .mif file.

--- Quote End ---

This works for the given example

module ram_with_init(
  output reg  q,
  input  d,
  input  write_address, read_address,
  input we, clk
);
  reg  mem ;
  integer i;
  initial begin
    for (i = 0; i < 32; i = i + 1)
      mem = i;
  end
  always @ (posedge clk) begin
    if (we)
      mem <= d;
    q <= mem;
  end
endmodule

But there seems to be a problem to convert multi-dimensional assignments as in your example. You can determine if the initial block has been converted correctly by reviewing the compilation messages. The INIT_FILE line will only appear if the initial block has been understood.

--- Quote Start ---

Info: Instantiated megafunction "altsyncram:ram_rtl_0" with the following parameter:

Info: Parameter "INIT_FILE" = "db/test1.ram0_single_port_ram_7cbe84f1.hdl.mif"

--- Quote End ---

Knowing this limitation, you'll hopefully find a workaround. You also may want to report this as a bug to Altera support.