Infer Large Multiplier in Stratix IV

I'm sorry to say that, in my experience so far, even if you generate LPM_MULT IP using the Quartus IP generator tool and explicitly request 3 or 4 internal register delays (depending on which FPGA family you're targeting -- I've been targeting both Arria 10 and Stratix 10), if retiming is on, it appears Quartus (15.1 and 16.1 both) will pull the internal registration out, gripe at you that your DSPs aren't fully registered, and then will never put it back, even when it's failing timing miserably and has plenty of other control/reset-free registers to work with. I've looked in vain for the "put my registers back where I left them!" button to no avail. If any other users have found a way to counteract this, I'd like to know, too.